Verilog program for parity generator

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We need to add the parity bit to a signal. This is done by the Parity generator. This parity inclusive binary message then transmits from transmitter to receiver end. If there is a change in the number of 1s at the receiving end, then that detects the presence of an error. Even parity is the case when the total number of 1s in the sum of data bits and parity bits is even whereas, in odd parity, it is odd. Remember this.

The binary sum of an even number of 1s is 0. And the sum of an odd number of 1s is 1. Now imagine a scenario. You want to send a stream of digital bits. You are slightly concerned with errors entering your message. You can either use the even parity mechanism. Or you can use the odd parity mechanism. Even parity mechanism : The target is to make the total number of 1s even. So we add a parity bit to make it two 1s. Now the number of 1s is even. Odd parity mechanism : Here, the target is the make the total number of 1s odd.

For example, consider the same message signal from above. The parity bit here will be…. Notice one thing? In this error detection method, the final message is the message you intended to send, plus one parity bit.

When the message reaches the destination, all we need to check is the parity bit if it is odd or even parity. Cross-reference that with what we knew at the transmitting end. And we can detect if an error is present. You can probably guess it by now.

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